1. Field of the Invention
The present invention relates to a semiconductor memory device having a redundant structure, and more particularly to a system for detecting the memory cell positions using the redundant structure.
2. Description of the Related Art
Memory capacity of semiconductor memory device has been remarkably increasing. With the increase in the capacity of semiconductor memories, redundant circuit technology has been introduced. The redundant circuit has a redundant column or row of memory cells which are added for a normal memory cell array and a redundant decoder for selecting the redundant column or row of memory cells. If the normal memory cell array contains any defective memory cells in a column or a row, the address corresponding to the defective column or row of memory cells is programmed into the redundant decoder in a known manner, thereby replacing the defective column or row of memory cells with the redundant column or row of memory cells, and thus enabling the defective chip to be relieved.
A memory device having such a redundant circuit involves necessity to know information about relief of the memory cell, that is whether or not the redundant circuit has been actually used, and the address of a defective part in the normal memory cell array which has been replaced with the redundant column or row, when the memory is evaluated or tested. Conventional practices therefor include a roll call circuit which is arranged such that a special circuit is provided in a memory chip to obtain relief information.
One approach for indicating whether the redundant circuit is actually used and which address of the normal memory array is replaced by the redundant structure is disclosed in the U.S. Pat. No. 4,731,759 issued to Watanabe. According to this U.S. Patent, a series circuit of field effect transistors is inserted between two power voltage terminals (Vcc and GND). The series circuit causes a DC current flowing the two power voltage when the redundant circuit is used for replacing the defective portion of the normal memory array. Therefore, by checking an amount of the DC current flowing through the two power voltage terminals, the usage of the redundant circuit can be known.
However, it is difficult to accurately measure the current flowing through the series circuit, because the memory circuit consumes an operating current which also flows between the two power voltage terminals. Moreover, the series circuit always consumes some current flowing therethrough at least when the memory circuit is enabled in a case where the redundant circuit is used. This consumes a wasteful power.